Deltasigma (ΔΣ; or sigmadelta, ΣΔ) modulation is an oversampling method for encoding signals into low bit depth digital signals at a very high samplefrequency as part of the process of deltasigma analogtodigital converters (ADCs) and digitaltoanalog converters (DACs). Deltasigma modulation achieves high quality by utilizing a negative feedback loop during quantization to the lower bit depth that continuously corrects quantization errors and moves quantization noise to higher frequencies well above the original signal's bandwidth. Subsequent lowpass filtering for demodulation easily removes this high frequency noise and time averages to achieve high accuracy in amplitude which can be ultimately encoded as pulsecode modulation (PCM).
Both ADCs and DACs can employ deltasigma modulation. A deltasigma ADC (e.g. Figure 1 top) encodes an analog signal using highfrequency deltasigma modulation and then applies a digital filter to demodulate it to a highbit digital output at a lower samplingfrequency. A deltasigma DAC (e.g. Figure 1 bottom) encodes a highresolution digital input signal into a lowerresolution but higher samplefrequency signal that may then be mapped to voltages and smoothed with an analog filter for demodulation. In both cases, the temporary use of a low bit depth signal at a higher sampling frequency simplifies circuit design and takes advantage of the efficiency and high accuracy in time of digital electronics.
Primarily because of its cost efficiency and reduced circuit complexity, this technique has found increasing use in modern electronic components such as DACs, ADCs, frequency synthesizers, switchedmode power supplies and motor controllers.^{[1]} The coarselyquantized output of a deltasigma ADC is occasionally used directly in signal processing or as a representation for signal storage (e.g., Super Audio CD stores the raw output of a 1bit deltasigma modulator).
While this article focuses on synchronous modulation, which requires a precise clock for quantization, asynchronous deltasigma modulation instead runs without a clock.
When transmitting an analog signal directly, all noise in the system and transmission is added to the analog signal, reducing its quality. Digitizing it enables noisefree transmission, storage, and processing. There are many methods of digitization.
In Nyquistrate ADCs, an analog signal is sampled at a relatively low sampling frequency just above its Nyquist rate (twice the signal's highest frequency) and quantized by a multilevel quantizer to produce a multibit digital signal. Such higherbit methods seek accuracy in amplitude directly, but require extremely precise components and so may suffer from poor linearity.
Oversampling converters instead produce a lowerbitdepth result at a much higher sampling frequency. This can achieve comparable quality by taking advantage of:
Another key aspect given by oversampling is the frequency/resolution tradeoff. The decimation filter put after the modulator not only filters the whole sampled signal in the band of interest (cutting the noise at higher frequencies), but also reduces the sampling rate, and hence the representable frequency range, of the signal, while increasing the sample amplitude resolution. This improvement in amplitude resolution is obtained by a sort of averaging of the higherdatarate bitstream.
Delta modulation is an earlier related lowbit oversampling method that also uses negative feedback, but only encodes the derivative of the signal (its delta) rather than its amplitude. The result is a stream of marks and spaces representing up or down of the signal's movement, which must be integrated to reconstruct the signal's amplitude. Delta modulation has several drawbacks. The differentiation alters the signal's spectrum by amplifying highfrequency noise, attenuating lowfrequencies,^{[2]} and dropping the DC component. This makes its dynamic range and SNR inversely proportional to signal frequency. Delta modulation suffers from slope overload if signals move too fast. And it is susceptible to transmission disturbances that result in cumulative error.
Deltasigma modulation rearranges the integrator and quantizer of a delta modulator, so that the output carries information corresponding to the amplitude of the input signal instead of just its derivative.^{[3]} This also has the benefit of incorporating desirable noise shaping into the conversion process, to deliberately move quantization noise to frequencies higher than the signal. Since the accumulated error signal is lowpass filtered by the deltasigma modulator's integrator before being quantized, the subsequent negative feedback of its quantized result effectively subtracts the low frequency components of the quantization noise while leaving the higher frequency components of the noise.
In the specific case of a singlebit synchronous ΔΣ ADC, an analog voltage signal is effectively converted into a pulse frequency, or pulse density, which can be understood as pulsedensity modulation (PDM). A sequence of positive and negative pulses, representing bits at a known fixed rate, is very easy to generate, transmit, and accurately regenerate at the receiver, given only that the timing and sign of the pulses can be recovered. Given such a sequence of pulses from a deltasigma modulator, the original waveform can be reconstructed with adequate precision.
The use of PDM as a signal representation is an alternative to PCM. Alternatively, the high frequency PDM can later be downsampled through a processed called decimation and requantized to convert it into a multibit PCM code at lower sampling frequency closer to the Nyquist rate of the frequency band of interest.
The seminal^{[4]} paper combining feedback with oversampling to achieve delta modulation was by F. de Jager of Philips Research Laboratories in 1952.^{[5]}
The principle of improving the resolution of a coarse quantizer by use of feedback, which is the basic principle of deltasigma conversion, was first described in a 1954filed patent by C. Chapin Cutler of Bell Labs.^{[6]} It was not named as such until a 1962 paper^{[7]} by Inose et al. of University of Tokyo, which came up with the idea of adding a filter in the forward path of the delta modulator.^{[8]}^{[note 1]} However, Charles B Brahm of United Aircraft Corp^{[9]} in 1961 filed a patent "Feedback integrating system"^{[10]} with a feedback loop containing an integrator with multibit quantization shown in its Fig 1.^{[2]}
Wooley's "The Evolution of Oversampling AnalogtoDigital Converters"^{[4]} gives more history and references to relevant patents. Some avenues of variation (which may be applied in different combinations) are the modulator's order, the quantizer's bitdepth, the manner of decimation, and the oversampling ratio.
Noise of the quantizer can be further shaped by replacing the quantizer itself with another ΔΣ modulator. This creates a 2^{nd}order modulator, which can be rearranged in a cascaded fashion (Figure 2).^{[2]} This process can be repeated to increase the order even more.
While 1^{st}order modulators are unconditionally stable, stability analysis must be performed for higherorder noisefeedback modulators. Alternatively, noisefeedforward configurations are always stable and have simpler analysis.^{[11]}^{§6.1}
The modulator can also be classified by the bit depth of its quantizer. A quantizer that distinguishes between Nlevels is called a log_{2}N bit quantizer. For example, a simple comparator has 2 levels and so is 1 bit quantizer; a 3level quantizer is called a "1.5" bit quantizer; a 4level quantizer is a 2bit quantizer; a 5level quantizer is called a 2.5bit quantizer.^{[12]} Higher bit quantizers inherently produce less quantization noise.
One criticism of 1bit quantization is that adequate amounts of dither cannot be used in the feedback loop, so distortion can be heard under some conditions (more discussion at Direct Stream Digital § DSD vs. PCM).^{[13]}^{[14]}
Decimation is strongly associated with deltasigma modulation, but is distinct and outside the scope of this article. The original 1962 paper didn't describe decimation. Oversampled data in the early days was sent as is. The proposal to decimate oversampled deltasigma data using digital filtering before converting it into PCM audio was made by D. J. Goodman at Bell Labs in 1969,^{[15]} to reduce the ΔΣ signal from its high sampling rate while increasing its bit depth. Decimation may be done in a separate chip on the receiving end of the deltasigma bit stream, sometimes by a dedicated module inside of a microcontroller,^{[16]} which is useful for interfacing with PDM MEMS microphones,^{[17]} though many ΔΣ ADC integrated circuits include decimation. Some microcontrollers even incorporate both the modulator and decimator.^{[18]}
Decimation filters most commonly used for ΔΣ ADCs, in order of increasing complexity and quality, are:
When a signal is quantized, the resulting signal can be approximated by addition of white noise with approximately equal intensity across the entire spectrum. In reality, the quantization noise is, of course, not independent of the signal and this dependence results in limit cycles and is the source of idle tones and pattern noise in deltasigma converters. However, adding dithering noise (Figure 3) reduces such distortion by making quantization noise more random.
ΔΣ ADCs reduce the amount of this noise in the baseband by spreading it out and shaping it so it is mostly in higher frequencies. It can then be easily filtered out with inexpensive digital filters, without highprecision analog circuits needed by Nyquist ADCs.
Quantization noise in the baseband frequency range (from DC to ) may be reduced by increasing the oversampling ratio (OSR) defined by
where is the sampling frequency and is the Nyquist rate (the minimum sampling rate needed to avoid aliasing, which is twice the original signal's maximum frequency ). Since oversampling is typically done in powers of two, represents how many times OSR is doubled.
As illustrated in Figure 4, the total amount of quantization noise is the same both in a Nyquist converter (yellow + green areas) and in an oversampling converter (blue + green areas). But oversampling converters distribute that noise over a much wider frequency range. The benefit is that the total amount of noise in the frequency band of interest is dramatically smaller for oversampling converters (just the small green area), than for a Nyquist converter (yellow + green total area).
Figure 4 shows how ΔΣ modulation shapes noise to further reduce the amount of quantization noise in the baseband in exchange for increasing noise at higher frequencies (where it can be easily filtered out). The curves of higherorder ΔΣ modulators achieve even greater reduction of noise in the baseband.
These curves are derived using mathematical tools called the Laplace transform (for continuoustime signals, e.g. in an ADC's modulation loop) or the Ztransform (for discretetime signals, e.g. in a DAC's modulation loop). These transforms are useful for converting harder math from the time domain into simpler math in the complex frequency domain of the complex variable (in the Laplace domain) or (in the zdomain).
Figure 5 represents the 1^{st}order ΔΣ ADC modulation loop (from Figure 1) as a continuoustime linear timeinvariant system in the Laplace domain with the equation:
The Laplace transform of integration of a function of time corresponds to simply multiplication by in Laplace notation. The integrator is assumed to be an ideal integrator to keep the math simple, but a real integrator (or similar filter) may have a more complicated expression.
The process of quantization is approximated as addition with a quantization error noise source. The noise is often assumed to be white and independent of the signal, though as quantization (signal processing) § Additive noise model explains that is not always a valid assumption (particularly for lowbit quantization).
Since the system and Laplace transform are linear, the total behavior of this system can be analyzed by separating how it affects the input from how it affects the noise:^{[11]}^{§6}
To understand how the system affect the input signal only, the noise is temporarily imagined to be 0:
which can be rearranged to yield the following transfer function:
This transfer function has a single pole at in the complex plane, so it effectively acts as a 1^{st}order lowpass filter on the input signal. (Note: its cutoff frequency could be adjusted as desired by including multiplication by a constant in the loop).
To understand how the system affects the noise only, the input instead is temporarily imagined to be 0:
which can be rearranged to yield the following transfer function:
This transfer function has a single zero at and a single pole at so the system effectively acts as a highpass filter on the noise that starts at 0 at DC, then gradually rises until it reaches the cutoff frequency, and then levels off.
The synchronous ΔΣ DAC's modulation loop (Figure 6) meanwhile is in discretetime and so its analysis is in the zdomain. It is very similar to the above analysis in Laplace domain and produces similar curves. Note: many sources^{[11]}^{§6.1}^{[25]}^{[26]} also analyze a ΔΣ ADC's modulation loop in the zdomain, which implicitly treats the continuous analog input as a discretetime signal. This may be a valid approximation provided that the input signal is already bandlimited and can be assumed to be not changing on time scales higher than the sampling rate. It is particularly appropriate when the modulator is implemented as a switched capacitor circuit, which work by transferring charge between capacitors in clocked time steps.
Integration in discretetime can be an accumulator which repeatedly sums its input with the previous result of its summation This is represented in the zdomain by feeding back a summing node's output though a 1clock cycle delay stage (notated as ) into another input of the summing node, yielding . Its transfer function is often used to label integrators in block diagrams.
In a ΔΣ DAC, the quantizer may be called a requantizer or a digitaltodigital converter (DDC), because its input is already digital and quantized but is simply reducing from a higher bitdepth to a lower bitdepth digital signal. This is represented in the zdomain by another delay stage in series with adding quantization noise. (Note: some sources may have swapped ordering of the and additive noise stages.)
The modulator's zdomain equation arranged like Figure 6 is: which can be rearranged to express the output in terms of the input and noise: The input simply comes out of the system delayed by one clock cycle. The noise term's multiplication by represents a first difference backward filter (which has a single pole at the origin and a single zero at ) and thus highpass filters the noise.
Without getting into the mathematical details,^{[25]}^{(equations 811)} cascading integrators to create an order modulator results in: Since this first difference backwards filter is now raised to the power it will have a steeper noise shaping curve, for improved properties of greater attenuation in the baseband, so a dramatically larger portion of the noise is above the baseband and can be easily filtered by an ideal lowpass filter.
The theoretical signaltonoise ratio (SNR) in decibels (dB) for a sinusoid input travelling through a order modulator with a OSR (and followed by an ideal lowpass decimation filter) can be mathematically derived to be approximately:^{[25]}^{(equations 1221)}
The theoretical effective number of bits (ENOB) resolution is thus improved by bits when doubling the OSR (incrementing ), and by bits when incrementing the order. For comparison, oversampling a Nyquist ADC (without any noise shaping) only improves its ENOB by bits for every doubling of the OSR,^{[27]} which is only 1⁄3 of the ENOB growth rate of a 1^{st}order ΔΣM.
Oversampling ratio  each OSR
doubling  

2^{4} OSR  2^{5} OSR  2^{6} OSR  2^{7} OSR  2^{8} OSR  
1^{st}order:

24 dB
3+3⁄4 bits 
33 dB
5+1⁄4 bits 
42 dB
6+3⁄4 bits 
51 dB
8+1⁄4 bits 
60 dB
9+3⁄4 bits 
+1+1⁄2 bits 
2^{nd}order:

39 dB
6+1⁄4 bits 
54 dB
8+3⁄4 bits 
69 dB
11+1⁄4 bits 
84 dB
13+3⁄4 bits 
99 dB
16+1⁄4 bits 
+2+1⁄2 bits 
3^{rd}order:

53 dB
8+3⁄4 bits 
75 dB
12+1⁄4 bits 
96 dB
15+3⁄4 bits 
117 dB
19+1⁄4 bits 
138 dB
22+3⁄4 bits 
+3+1⁄2 bits 
4^{th}order:

68 dB
11+1⁄4 bits 
95 dB
15+3⁄4 bits 
112 dB
20+1⁄4 bits 
149 dB
24+3⁄4 bits 
177 dB
29+1⁄2 bits 
+4+1⁄2 bits 
5^{th}order:

83 dB
13+1⁄2 bits 
116 dB
19 bits 
149 dB
24+1⁄2 bits 
182 dB
30 bits 
215 dB
35+1⁄2 bits 
+5+1⁄2 bits 
6^{th}order:

99 dB
16 bits 
137 dB
22+1⁄2 bits 
176 dB
29 bits 
215 dB
35+1⁄2 bits 
254 dB
42 bits 
+6+1⁄2 bits 
each additional order:

+2+1⁄2 bits  +3+1⁄2 bits  +4+1⁄2 bits  +5+1⁄2 bits  +6+1⁄2 bits 
These datapoints are theoretical. In practice, circuits inevitably experience other noise sources that limit resolution, making the higherresolution cells impractical.
Deltasigma modulation is related to delta modulation by the following steps (Figure 7):^{[11]}^{§6}
If quantization were homogeneous (e.g., if it were linear), the above would be a sufficient derivation of their hypothetical equivalence. But because the quantizer is not homogeneous, deltasigma is inspired by delta modulation, but the two are distinct in operation.
From the first block diagram in Figure 7, the integrator in the feedback path can be removed if the feedback is taken directly from the input of the lowpass filter. Hence, for delta modulation of input signal v_{in}, the lowpass filter sees the signal
However, deltasigma modulation of the same input signal places at the lowpass filter
In other words, doing deltasigma modulation instead of delta modulation has effectively swapped the ordering of the integrator and quantizer operations. The net effect is a simpler implementation that has the profound added benefit of shaping the quantization noise to be mostly in frequencies above the signals of interest. This effect becomes more dramatic with increased oversampling, which allows for quantization noise to be somewhat programmable. On the other hand, delta modulation shapes both noise and signal equally.
Additionally, the quantizer (e.g., comparator) used in delta modulation has a small output representing a small step up and down the quantized approximation of the input while the quantizer used in deltasigma must take values outside of the range of the input signal.
In general, deltasigma has some advantages versus delta modulation:
Deltasigma ADCs vary in complexity. The below circuit focuses on a simple 1storder, 2level quantization synchronous deltasigma ADC without decimation.
To ease understanding, a simple circuit schematic (Figure 8a) using ideal elements is simulated (Figure 8b voltages). It is functionally the same AnalogtoDigital ΔΣ modulation loop in Figure 1 (note: the 2input inverting integrator combines the summing junction and integrator and produces a negative feedback result, and the flipflop combines the sampled quantizer and conveniently naturally functions as a 1bit DAC too).
The 20 kHz input sine wave s(t) is converted to a 1bit PDM digital result Q(t). 20 kHz is used as an example because that is considered the upper limit of human hearing.
This circuit can be laid out on a breadboard with inexpensive discrete components (note some variations use different biasing and use simpler RC lowpass filters for integration instead of op amps).^{[28]}^{[29]}
For simplicity, the D flipflop is powered by dual supply voltages of V_{DD} = +1 V and V_{SS} = 1 V, so its binary output Q(t) is either +1 V or 1 V.
The 2input inverting op amp integrator combines s(t) with Q(t) to produce Ɛ(t): The Greek letter epsilon is used because Ɛ(t) contains the accumulated error that is repeatedly corrected by the feedback mechanism. While both its inputs s(t) and Q(t) vary between 1 and 1 volts, Ɛ(t) instead only varies by a couple millivolts about 0 V.
Because of the integrator's negative sign, when Ɛ(t) next gets sampled to produce Q(t), the +Q(t) in this integral actually represents negative feedback from the previous clock cycle.
An ideal D flipflop samples Ɛ(t) at the clock rate of 1 MHz. The scope view (Figure 8b) has a minor division equal to the sampling period of 1 μs, so every minor division corresponds to a sampling event. Since the flipflop is assumed to be ideal, it treats any input voltage greater than 0 V as logical high and any input voltage smaller than 0 V as logical low, no matter how close it is to 0 V (ignoring issues of sampleandhold time violations and metastability).
Whenever a sampling event occurs:
Q(t) is sent out as the resulting PDM output and also fed back to the 2input inverting integrator.
The rightmost integrator performs digitaltoanalog conversion on Q(t) to produce a demodulated analog output r(t), which reconstructs the original sine wave input as piecewise linear diagonal segments. Although r(t) appears coarse at this 50x oversampling rate, r(t) can be lowpass filtered to isolate the original signal. As the sampling rate is increased relative to the input signal's maximum frequency, r(t) will more closely approximate the original input s(t).
It is worth noting that if no decimation ever took place, the digital representation from a 1bit deltasigma modulator is simply a PDM signal, which can easily be converted to analog using a lowpass filter, as simple as a resistor and capacitor.^{[29]}
However, in general, a deltasigma DAC converts a discrete time series signal of digital samples at a highbitdepth into a lowbitdepth (often 1bit) signal, usually at a much higher sampling rate. That deltamodulated signal can then be accurately converted into analog (since lower bitdepth DACs are easier to be highlylinear), which then goes through inexpensive lowpass filtering in the analog domain to remove the highfrequency quantization noise inherent to the deltasigma modulation process.
As the discrete Fourier transform and discretetime Fourier transform articles explain, a periodicallysampled signal inherently contains multiple higher frequency copies or "images" of the signal. It is often desirable to remove these higherfrequency images prior to the performing the actual deltasigma modulation stage, in order to ease requirements on the eventual analog lowpass filter. This can be done by upsampling using an interpolation filter and is often the first step prior to performing deltasigma modulation in DACs. Upsampling is strongly associated with deltasigma DACs but not strictly part of the actual deltasigma modulation stage (similar to how decimation is strongly associated with deltasigma ADCs but not strictly part of deltasigma modulation either), and the details are out of the scope of this article.
The modulation loop in Figure 6 in § Noise shaping can easily be laid out with basic digital elements of a subtractor for the difference, an accumulator for the integrator, and a lowerbit register for the quantization, which carries over the mostsignificant bit(s) from the integrator to be the feedback for the next cycle.
This simple 1^{st}order modulation can be improved by cascading two or more overflowing accumulators, each of which is equivalent to a 1^{st}order deltasigma modulator. The resulting multistage noise shaping (MASH)^{[30]} structure has a steeper noise shaping property, so is commonly used in digital audio. The carry outputs are combined through summations and delays to produce a binary output, the width of which depends on the number of stages (order) of the MASH. Besides its noise shaping function, it has two more attractive properties:
The technique was first presented in the early 1960s by professor Yasuhiko Yasuda while he was a student at the University of Tokyo.^{[31]}^{[11]} The name deltasigma comes directly from the presence of a delta modulator and an integrator, as firstly introduced by Inose et al. in their patent^{[clarification needed]} application.^{[7]} That is, the name comes from integrating or summing differences, which, in mathematics, are operations usually associated with Greek letters sigma and delta respectively.
In the 1970s, Bell Labs engineers used the terms "sigmadelta" because the precedent was to name variations on delta modulation with adjectives preceding "delta", and an Analog Devices magazine editor justified in 1990 that the functional hierarchy is "sigmadelta", because it computes the integral of a difference.^{[32]}
Both names sigmadelta and deltasigma are frequently used.
Kirkkert and Miller published a continuoustime variant called "Asynchronous Delta Sigma Modulation" (ADSM or ASDM) in 1975 which uses either a Schmitt trigger (i.e. a comparator with hysteresis) or (as the paper argues is equivalent) a comparator with fixed delay.^{[33]}
In the example in Figure 9, when the integral of the error exceeds its limits, the output changes state, producing a pulsewidth modulated (PWM) output wave.
Amplitude information is converted, without quantization noise, into time information of the output PWM.^{[34]} To convert this continuous time PWM to discrete time, the PWM may be sampled by a timetodigital converter, whose limited resolution adds noise which can be shaped by feeding it back.^{[35]}