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Gem5

Summary

The gem5 simulator is an open-source system-level and processor simulator. It is utilized in academic research and in industry by companies such as ARM Research, AMD Research, Google, Micron, Metempsy, HP, and Samsung.[1][2] Arm has developed further software called Streamline for developers working with gem5 which aims to present "a graphical view of system execution".[3]

gem5
Developer(s)Community
Initial releaseAugust 2011; 12 years ago (2011-08)
Stable release
v23.1 / December 21, 2023; 4 months ago (2023-12-21)
Written inC++, Python
Operating systemLinux
LicenseRevised BSD License
Websitewww.gem5.org


History edit

The gem5 simulator was born out of the merger of m5 (CPU simulation framework) and GEMS (memory timing simulator).[4]

Features edit

gem5 is an event-driven simulator with multiple execution modes.[4]

  • full-system emulation (simulating the whole OS) and syscall emulation (just user-space is emulated)
  • multiple ISAs (Alpha, ARM, SPARC, MIPS, POWER, RISC-V, and x86 ISAs)[1]
  • timing model for the full cache hierarchy with support for custom coherence protocols
  • simplistic CPU, in-order CPU, out-of-order CPU
  • serialize/deserialization from checkpoints

References edit

  1. ^ a b "gem5: About". Retrieved 14 November 2019.
  2. ^ "Simulation Research and gem5". Davis Architecture Research. Retrieved 22 June 2022.
  3. ^ "Streamline for gem5". Arm Developer. Retrieved 22 June 2022.
  4. ^ a b Binkert, Nathan; Sardashti, Somayeh; Sen, Rathijit; Sewell, Korey; Shoaib, Muhammad; Vaish, Nilay; Hill, Mark D.; Wood, David A.; Beckmann, Bradford; Black, Gabriel; Reinhardt, Steven K. (2011-08-31). "The gem5 simulator". ACM SIGARCH Computer Architecture News. 39 (2): 1–7. doi:10.1145/2024716.2024718. S2CID 195349294.

External links edit

  • Official website
  • Source code