The memory cell is the fundamental building block of computer memory. The memory cell is an electronic circuit that stores one bit of binary information and it must be set to store a logic 1 (high voltage level) and reset to store a logic 0 (low voltage level). Its value is maintained/stored until it is changed by the set/reset process. The value in the memory cell can be accessed by reading it.
Layout for the silicon implementation of a six transistor SRAM memory cell.
The SRAM (static RAM) memory cell is a type of flip-flop circuit, typically implemented using MOSFETs. These require very low power to keep the stored value when not being accessed. A second type, DRAM (dynamic RAM), is based around MOS capacitors. Charging and discharging a capacitor can store a '1' or a '0' in the cell. However, the charge in this capacitor will slowly leak away, and must be refreshed periodically. Because of this refresh process, DRAM uses more power. However, DRAM can achieve greater storage densities.
The memory cell is the fundamental building block of memory. It can be implemented using different technologies, such as bipolar, MOS, and other semiconductor devices. It can also be built from magnetic material such as ferrite cores or magnetic bubbles. Regardless of the implementation technology used, the purpose of the binary memory cell is always the same. It stores one bit of binary information that can be accessed by reading the cell and it must be set to store a 1 and reset to store a 0.
Square array of DRAM memory cells being read
Logic circuits without memory cells are called combinational, meaning the output depends only on the present input.
But memory is a key element of digital systems. In computers, it allows to store both programs and data and memory cells are also used for temporary storage of the output of combinational circuits to be used later by digital systems.
Logic circuits that use memory cells are called sequential circuits, meaning the output depends not only on the present input, but also on the history of past inputs.
This dependence on the history of past inputs makes these circuits stateful and it is the memory cells that store this state.
These circuits require a timing generator or clock for their operation.
Computer memory used in most contemporary computer systems is built mainly out of DRAM cells; since the layout is much smaller than SRAM, it can be more densely packed yielding cheaper memory with greater capacity. Since the DRAM memory cell stores its value as the charge of a capacitor, and there are current leakage issues, its value must be constantly rewritten. This is one of the reasons that make DRAM cells slower than the larger SRAM (static RAM) cells, which has its value always available. That is the reason why SRAM memory is used for on-chipcache included in modern microprocessor chips.
SRAM typically has six-transistor cells, whereas DRAM (dynamic random-access memory) typically has single-transistor cells. In 1965, Toshiba's Toscal BC-1411 electronic calculator used a form of capacitive bipolar DRAM, storing 180-bit data on discrete memory cells, consisting of germanium bipolar transistors and capacitors. MOS technology is the basis for modern DRAM. In 1966, Dr. Robert H. Dennard at the IBM Thomas J. Watson Research Center was working on MOS memory. While examining the characteristics of MOS technology, he found it was capable of building capacitors, and that storing a charge or no charge on the MOS capacitor could represent the 1 and 0 of a bit, while the MOS transistor could control writing the charge to the capacitor. This led to his development of a single-transistor DRAM memory cell. In 1967, Dennard filed a patent for a single-transistor DRAM memory cell, based on MOS technology.
The first commercial bipolar 64-bit SRAM was released by Intel in 1969 with the 3101 SchottkyTTL. One year later, it released the first DRAM integrated circuit chip, the Intel 1103, based on MOS technology. By 1972, it beat previous records in semiconductor memory sales. DRAM chips during the early 1970s had three-transistor cells, before single-transistor cells became standard since the mid-1970s.
CMOS memory was commercialized by RCA, which launched a 288-bit CMOS SRAM memory chip in 1968. CMOS memory was initially slower than NMOS memory, which was more widely used by computers in the 1970s. In 1978, Hitachi introduced the twin-well CMOS process, with its HM6147 (4kb SRAM) memory chip, manufactured with a 3 µm process. The HM6147 chip was able to match the performance of the fastest NMOS memory chip at the time, while the HM6147 also consumed significantly less power. With comparable performance and much less power consumption, the twin-well CMOS process eventually overtook NMOS as the most common semiconductor manufacturing process for computer memory in the 1980s.
The two most common types of DRAM memory cells since the 1980s have been trench-capacitor cells and stacked-capacitor cells. Trench-capacitor cells are where holes (trenches) are made in a silicon substrate, whose side walls are used as a memory cell, whereas
stacked-capacitor cells are the earliest form of three-dimensional memory (3D memory), where memory cells are stacked vertically in a three-dimensional cell structure. Both debuted in 1984, when Hitachi introduced trench-capacitor memory and Fujitsu introduced stacked-capacitor memory.
The following schematics detail the three most used implementations for memory cells :
The dynamic random access memory cell (DRAM);
The static random access memory cell (SRAM);
Flip-flops like the J/K shown below.
DRAM cell (1 transistor and one capacitor).
SRAM cell (6 transistors).
Clocked J/K flip-flop.
DRAM memory cellEdit
Die of the MT4C1024 (1994) integrating one-mebibit of DRAM memory cells.
The storage element of the DRAM memory cell is the capacitor labeled (4) in the diagram above. The charge stored in the capacitor degrades over time, so its value must be refreshed (read and rewritten) periodically. The nMOS transistor (3) acts as a gate to allow reading or writing when open or storing when closed.
For reading the Word line (2) drives a logic 1 (voltage high) into the gate of the nMOS transistor (3) which makes it conductive and the charge stored at the capacitor (4) is then transferred to the bit line (1). The bit line will have a parasitic capacitance (5) that will drain part of the charge and slow the reading process. The capacitance of the bit line will determine the needed size of the storage capacitor (4). It is a trade-off. If the storage capacitor is too small, the voltage of the bit line would take too much time to raise or not even rise above the threshold needed by the amplifiers at the end of the bit line. Since the reading process degrades the charge in the storage capacitor (4) its value is rewritten after each read.
The writing process is the easiest, the desired value logic 1 (high voltage) or logic 0 (low voltage) is driven into the bit line. The word line activates the nMOS transistor (3) connecting it to the storage capacitor (4). The only issue is to keep it open enough time to ensure that the capacitor is fully charged or discharged before turning off the nMOS transistor (3).
SRAM memory cellEdit
SRAM memory cell depicting Inverter Loop as gates
An animated SR latch. Black and white mean logical '1' and '0', respectively. (A) S = 1, R = 0: set (B) S = 0, R = 0: hold (C) S = 0, R = 1: reset (D) S = 1, R = 1: not allowed Transitioning from the restricted combination (D) to (A) leads to an unstable state.
The working principle of SRAM memory cell can be easier to understand if the transistors M1 through M4 are drawn as logic gates. That way it is clear that at its heart, the cell storage is built by using two cross-coupled inverters. This simple loop creates a bi-stable circuit. A logic 1 at the input of the first inverter turns into a 0 at its output, and it is fed into the second inverter which transforms that logic 0 back to a logic 1 feeding back the same value to the input of the first inverter. That creates a stable state that does not change over time. Similarly the other stable state of the circuit is to have a logic 0 at the input of the first inverter. After been inverted twice it will also feedback the same value.
Therefore there are only two stable states that the circuit can be in:
= 0 and = 1
= 1 and = 0
To read the contents of the memory cell stored in the loop, the transistors M5 and M6 must be turned on. when they receive voltage to their gates from the word line (), they become conductive and so the and values get transmitted to the bit line () and to its complement (). Finally this values get amplified at the end of the bit lines.
The writing process is similar, the difference is that now the new value that will be stored in the memory cell is driven into the bit line () and the inverted one into its complement (). Next transistors M5 and M6 are open by driving a logic 1 (voltage high) into the word line (). This effectively connects the bit lines to the by-stable inverter loop. There are two possible cases:
If the value of the loop is the same as the new value driven, there is no change;
if the value of the loop is different from the new value driven there are two conflicting values, in order for the voltage in the bit lines to overwrite the output of the inverters, the size of the M5 and M6 transistors must be larger than that of the M1-M4 transistors. This allows more current to flow through first ones and therefore tips the voltage in the direction of the new value, at some point the loop will then amplify this intermediate value to full rail.
The flip-flop has many different implementations, its storage element is usually a latch consisting of a NAND gate loop or a NOR gate loop with additional gates used to implement clocking. Its value is always available for reading as an output. The value remains stored until it is changed through the set or reset process. Flip-flops are typically implemented using MOSFETs.
A floating-gate memory cell is basically an MOS transistor with a gate completely surrounded by dielectrics (Fig. 1.2), the floating-gate (FG), and electrically governed by a capacitive-coupled control-gate (CG). Being electrically isolated, the FG acts as the storing electrode for the cell device. Charge injected into the FG is maintained there, allowing modulation of the ‘apparent’ threshold voltage (i.e. VT seen from the CG) of the cell transistor.
^Kent, Allen; Williams, James G. (6 January 1992). Encyclopedia of microcomputers: volume 9 - Icon programming language to knowledge-based systems: APL techniques. CRC press. p. 131. ISBN 9780824727086.
^"Toshiba: Inventor of flash memory". Toshiba. Archived from the original on 20 June 2019. Retrieved 20 June 2019.
^Masuoka, F.; Momodomi, M.; Iwata, Y.; Shirota, R. (1987). "New ultra high density EPROM and flash EEPROM with NAND structure cell". Electron Devices Meeting, 1987 International. IEDM 1987. IEEE. doi:10.1109/IEDM.1987.191485.
^"Toshiba announces new "3D" NAND flash technology". Engadget. 12 June 2007. Retrieved 10 July 2019.
^"Samsung introduces world's first 3D V-NAND based SSD for enterprise applications". Samsung semiconductor global website. Archived from the original on 15 April 2021.
^Clarke, Peter (2013). "Samsung confirms 24 layers in 3D NAND". EE Times.
^Jacob, Bruce; Ng, Spencer; Wang, David (28 July 2010). Memory systems: Cache, DRAM, disk. Morgan Kaufmann. p. 355. ISBN 9780080553849.
^ abSiddiqi, Muzaffer A. (19 December 2012). Dynamic RAM: Technology advancements. CRC Press. p. 10. ISBN 9781439893739.
^ abcdLi, Hai; Chen, Yiran (19 April 2016). Nonvolatile memory design: Magnetic, resistive, and phase change. CRC press. pp. 6, 7. ISBN 9781439807460.