In lower frequency (slow edge rate) applications, interconnection lines can be modelled as "lumped" circuits. In this case, there is no need to consider the concept of "termination". Under the low-frequency condition, every point in an interconnect wire can be assumed to have the same voltage as every other point for any instance in time.

However, if the propagation delay in a wire, PCB trace, cable, or connector is significant (for example, if the delay is greater than 1/6 of the rise time of the digital signal), the "lumped" circuit model is no longer valid and the interconnect has to be analyzed as a transmission line. In a transmission line, the signal interconnect path is modeled as a circuit containing distributed inductance, capacitance, and resistance throughout its length.

For a transmission line to minimize distortion of the signal, the impedance of every location on the transmission line should be uniform throughout its length. If there is any place in the line where the impedance is not uniform for some reason (open circuit, impedance discontinuity, different material) the signal gets modified by reflection at the impedance change point which results in distortion, ringing, and so forth.

When the signal path has impedance discontinuity, in other words, an impedance mismatch, then a termination impedance with the equivalent amount of impedance is placed at the point of line discontinuity. This is described as "termination". For example, resistors can be placed on computer motherboards to terminate high-speed busses. There are several ways of termination depending on how the resistors are connected to the transmission line. Parallel termination and series termination are examples of termination methodologies.

Instead of having the necessary resistive termination located on the motherboard, the termination is located inside the semiconductor chips–technique called On-Die Termination (abbreviated to ODT).

Why is on-die termination needed? edit

Although the termination resistors on the motherboard reduce some reflections on the signal lines, they are unable to prevent reflections resulting from the stub lines that connect to the components on the module card (e.g. DRAM module). A signal propagating from the controller to the components encounters an impedance discontinuity at the stub leading to the components on the module. The signal that propagates along the stub to the component (e.g. DRAM component) will be reflected onto the signal line, thereby introducing unwanted noise into the signal. In addition, on-die termination can reduce the number of resistor elements and complex wiring on the motherboard. Accordingly, the system design can be simpler and cost-effective.

Example of ODT: DRAM edit

On-die termination is implemented with several combinations of resistors on the DRAM silicon along with other circuit trees. DRAM circuit designers can use a combination of transistors that have different values of turn-on resistance. In the case of DDR2, there are three kinds of internal resistors 150ohm, 75ohm, and 50ohm. The resistors can be combined to create a proper equivalent impedance value to the outside of the chip, whereby the signal line (transmission line) of the motherboard is controlled by the on-die termination operation signal. Where an on-die termination value control circuit exists the DRAM controller manages the on-die termination resistance through a programmable configuration register that resides in the DRAM. The internal on-die termination values in DDR3 are 120ohm, 60ohm, 40ohm, and so forth.

How On-Die Termination (ODT) Works: An Example of DRAM^[1] edit

Utilizing On-Die Termination (ODT) involves two steps. First, the On-Die Termination (ODT) value must be selected within the DRAM. Second, it can be dynamically enabled/disabled using the ODT pin from the ODT Controller. To configure ODT there could be different methods. In DRAM, it is done by setting up the device’s extended mode register with the proper ODT value.

There are synchronous and asynchronous timing requirements, depending on the state of the DRAM device. Essentially, the On-Die Termination (ODT) is turned on just before the data transfer and then shut off immediately after. If there is more than one DRAM device loaded on the channel, either the active or inactive DRAM can terminate the signal. This flexibility enables optimal termination to occur as precisely as needed.

Let’s try to understand how On-Die Termination (ODT) works in DRAM read and write operations. All data-group signals fall under point-to-point singling. The data-group signals are driven by the DRAM controller on writes and driven by the DRAM memories during reads. No external resistors are needed on these routes on PCB as the DRAM controller and Memory are equipped with ODT. The receivers in both cases (DRAMS memory on writes and DRAM controller on reads) will assert on-die terminations (ODT) at the appropriate times. The following diagrams show the impedances seen on these nets during write and read cycles.

On-Die Termination (ODT) in Write Cycle edit

Let’s take an example of the impedances seen on the nets during a write cycle as per the below picture. During writes, the output impedance of the DRAM device is approximately 45Ω. It is recommended that the SDRAM be implemented with a 240Ω. Assuming the RZQ resistor is 240Ω, Termination resistors can be configured to present an On-Die Termination (ODT) of RZQ/4 for an effective termination of 40Ω.

On-die Termination (ODT) in Read Cycle edit

The picture shows the impedances seen on the PCB nets during a read cycle. During reads, it is recommended that the DRAM be configured for an effective drive impedance of RZQ/7 or 34 Ω (assuming the RZQ resistor is 240 Ω). The on-die termination (ODT) within the DRAM controller will have an effective Thevenin impedance of 45 Ω.

Fly-By Signals edit

Now let’s talk about the fly-by signals, which include the address, control, command, and clock routing groups. The fly-by signals consist of the fly-by routing from the DRAM controller, stubs at each SDRAM, and terminations after the last SDRAM. In this example, address, control, and command groups will be terminated through a 39.2-2 resistor to VTT.

The clock pairs will be terminated through 39.2Ω resistors to a common node connected to a capacitor that is then connected to VDDQ. The DRAM controller will present a 45-2 output impedance when driving these signals.

• Reflections of signals on conducting lines

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