A priority-encoder, also called leading zero detector (LZD) or leading zero counter (LZC), receives an ${\displaystyle n}$ -bit input vector and detects the index of the first binary ‘1’ in the input vector. A valid signal indicates if any binary ‘1’ was detected in the input vector, hence the index is valid.

Priority-encoders can be efficiently constructed by recursion. The input vector is split into ${\displaystyle k}$  equal fragments with ${\displaystyle n/k}$  bits. A priority encoder ${\displaystyle {\textrm {PE}}_{n/k}}$  with a narrower width of 𝑛/𝑘 is applied for each fragment. The valid bit of each of the ${\displaystyle k}$  ${\displaystyle {\textrm {PE}}_{n/k}}$ ‘s goes to a ${\displaystyle k}$  bit ${\displaystyle {\textrm {PE}}_{n/k}}$  to detect the first valid fragment. The location of this fragment is the higher part of the overall index, and steers the exact location within the fragment itself to produce the lower part of the overall index.

The depth of the proposed structure is ${\displaystyle \lceil \log _{k}n\rceil }$ , while the hardware area complexity is ${\displaystyle {\mathcal {O}}(n)}$ . If Altera's Stratix V or equivalent device is used, ${\displaystyle k=4}$  is recommended to achieve higher performance and area compression, since the mux can be implemented using 6-LUT, hence an entire ALM.

An open-source Verilog generator for the recursive priority-encoder is available online.^[6]

A behavioral description of priority encoder in Verilog is as follows.^[6]

// behavioural description of priority enconder;
// https://github.com/AmeerAbdelhadi/Indirectly-Indexed-2D-Binary-Content-Addressable-Memory-BCAM

module pe_bhv
 #( parameter                   OHW = 512 ) // encoder one-hot input width
  ( input                       clk       , // clock for pipelined priority encoder
    input                       rst       , // registers reset for pipelined priority encoder
    input      [      OHW -1:0] oht       ,  // one-hot input  / [      OHW -1:0]
    output reg [`log2(OHW)-1:0] bin       ,  // first '1' index/ [`log2(OHW)-1:0]
    output reg                  vld       ); // binary is valid if one was found
    
  // use while loop for non fixed loop length
  // synthesizable well with Intel's QuartusII
  always @(*) begin
    bin = {`log2(OHW){1'b0}};
    vld = oht[bin]         ;
    while ((!vld) && (bin!=(OHW-1))) begin
      bin = bin + 1 ;
      vld = oht[bin];
    end
  end

endmodule

A simple encoder circuit is a one-hot to binary converter. That is, if there are 2ⁿ input lines, and at most only one of them will ever be high, the binary code of this 'hot' line is produced on the n-bit output lines.